Staff Engineer - ASIC Physical Design

Micron Technology
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["English proficiency","Collaboration","Interpersonal skills","Analytical skills","Problem-solving"]

Work on processors, controller architectures, and ASICs for Enterprise SSDs, driving physical design from floorplanning through tape-out. Own block-level low-power aware planning, PPA and STA closure, clock-tree synthesis, routing, RC extraction, and timing closure. Perform IR/EM analysis, physical verification (DRC/LVS/ERC/antenna), and resolve IR issues based on feedback. Collaborate using Cadence (Innovus/Tempus) and Caliber tools, applying advanced-node expertise and AI-assisted workflows to improve execution.

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FursaFursa
Micron Technology
Micron Technology
4 weeks ago

Staff Engineer - ASIC Physical Design

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Last checked: 17 hours agoStatus: Live

Job Summary

Work on processors, controller architectures, and ASICs for Enterprise SSDs, driving physical design from floorplanning through tape-out. Own block-level low-power aware planning, PPA and STA closure, clock-tree synthesis, routing, RC extraction, and timing closure. Perform IR/EM analysis, physical verification (DRC/LVS/ERC/antenna), and resolve IR issues based on feedback. Collaborate using Cadence (Innovus/Tempus) and Caliber tools, applying advanced-node expertise and AI-assisted workflows to improve execution.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Deliver ASIC physical design work for Enterprise SSD group processors, controller architectures, and ASICs.
  • •Execute block-level low power aware floorplanning, placement, CTS, routing, RC extraction, and support STA timing closure.
  • •Develop and apply APR flow, perform PPA analysis, and drive closure to tape-out activities.
  • •Run physical verification using DRC/LVS/ERC (and antenna) and close issues to closure.
  • •Analyze and close IR/EM issues within blocks using feedback and ensure strong digital fundamentals execution.

Key Requirements

  • •Minimum of 8 years of hands-on ASIC physical design implementation experience, including APR flow development and PPA analysis with STA closure at block level.
  • •Proficiency in block-level low power aware floorplanning, placement, clock tree synthesis, routing, RC extraction, and tape-out activities.
  • •Experience with AI-assisted workflows for physical design execution.
  • •Advanced process node experience (5nm/3nm preferred).
  • •Hands-on physical verification closure (DRC/LVS/Antenna) using Caliber, and strong IR/EM issue closure within blocks based on feedback.
Experience:8+ years
Education:Bachelor's in electronics and computer architecture
Skills:English proficiencyCollaborationInterpersonal skillsAnalytical skillsProblem-solving
Languages:English
Tech Stack:Cadence InnovusCadence TempusCadence PnRAPR flowPPA analysisSTA timing closureAI toolsCaliberDRCLVSERCAntennaIR/EM analysisClock tree synthesisRC extractionTape out

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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Glassdoor: 3.7
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