ASIC Physical Design Engineer — Synthesis and Timing – (Associate or Experienced)
United States
Workplace: OnsiteFull timeUSD 98,600 - 162,150 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: bachelorsSkills: ["Analytical","Problem-solving","Communication","Autonomous"]Own portions of the ASIC physical design flow for mission-critical satellite and space SoCs, spanning synthesis and static timing analysis through ECO implementation and tapeout readiness. Partner with RTL, verification, DFT, and backend teams to ensure clean netlist handoffs and reliable timing/power convergence. Build methodology and automation, evaluate tools, and troubleshoot complex cross-domain timing issues while supporting chip-level integration and signoff activities.
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