ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)

Lead verification for ASIC design in Cisco's Silicon Photonics team. Oversee block and full-chip verification using SystemVerilog, UVM, Python, and C; develop testbenches, coverage, and ATE planning, collaborating across RTL, FPGA, and CPU subsystems to deliver high-speed optical transceivers for data center platforms.