Lead Customer Engagement Engineer

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 119,000 - 221,000 annuallyFunction: Administration & Executive AssistanceExperience: 5+ yearsEducation: bachelorsSkills: ["Communication","Problem-solving"]

Work with the HSV Customer Support team to provide technical support for Palladium, Protium, and Virtual Protocol (PDAPP) products. Triage and resolve product issues reported by field AE teams and customers, reproduce failures with test cases, and partner with HSV R&D to validate fixes and enhancements. Support customer requests, test new features for upcoming releases, and communicate complex debugging outcomes clearly to both customers and internal teams.

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Cadence Design Systems
Cadence Design Systems
1 day ago

Lead Customer Engagement Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Work with the HSV Customer Support team to provide technical support for Palladium, Protium, and Virtual Protocol (PDAPP) products. Triage and resolve product issues reported by field AE teams and customers, reproduce failures with test cases, and partner with HSV R&D to validate fixes and enhancements. Support customer requests, test new features for upcoming releases, and communicate complex debugging outcomes clearly to both customers and internal teams.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Take ownership of product issues reported by field AEs and customers and drive them to resolution.
  • •Debug customer-reported failures by producing test cases to replicate issues and logging them with HSV R&D teams.
  • •Recommend workarounds or application-level solutions when needed by customers.
  • •Test R&D fixes/patches and help spec out enhancement requests with customers and internal groups.
  • •Test new product features for future software releases or hardware platforms, including participation in internal beta activities.
Travel: Low travel

Pay and Benefits

Salary: USD 119,000 - 221,000 annually
Equity and Bonus:Equity
Perks:Paid Leave401kEquityMedicalDentalVision

Key Requirements

  • •BS in EE/CE (MS in EE/CE preferred) with at least 5 years of experience in design and/or verification of complex digital designs or an applications engineering/technical support role.
  • •Strong knowledge of design debugging techniques and logic design fundamentals.
  • •Knowledge of verification methodologies for complex EDA environments.
  • •Proficiency in HDL languages including Verilog, SystemVerilog, and VHDL, with ability to create test cases to replicate customer issues quickly.
  • •Proficiency in Unix/Linux scripting (ksh/bash/csh) and understanding of PCIe, USB, and Ethernet protocol. UVM experience is a plus.
Experience:5+ yearsEDADigital designVerificationApplications engineering
Education:Bachelor's in EE/CE
Skills:CommunicationProblem-solving
Tech Stack:PalladiumProtiumVirtual Protocol (PDAPP)HDLVerilogSystemVerilogVHDLUnixLinuxKshBashCshPCIeUSBEthernetTBASVASV coverageLow PowerUPF

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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