NVIDIA

1 month ago

Senior ASIC Floorplan Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Senior ASIC Floorplan Engineer to lead chip floorplanning for SOCs/CPUs/GPUs, collaborating with multi-disciplinary teams from architecture to physical design. Drive floorplan development, optimize area, power and timing, and build AI-enabled workflows to accelerate design. Requires 10+ years in chip development, strong communication, and expertise in ASIC floorplanning and physical design methodologies.

Location: Santa Clara, Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Collaborate with product managers, chip architects, ASIC design, physical design, and packaging teams to craft chip floorplans that optimize cost/area, performance, and power for target markets
•Drive floorplan development and work with ASIC/Physical Design teams to identify and solve area, interconnect, timing, and floorplan improvement opportunities
•Develop AI workflows and productivity tools to improve infrastructure for optimizing chip area and speed of execution
•Identify key technical and product risks and work with engineering and management to implement risk mitigation strategies
•Communicate progress and options to align multiple multidisciplinary teams on floorplan decisions

Pay and Benefits

Salary: USD 196,000 - 310,500 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•MSEE/MSCE (or equivalent) with broad and deep experience in chip development
•10+ years of experience
•Experience with developing SOC, CPU, graphics, memory, and I/O sub-systems in the chip
•Ability to multi-task across simultaneous projects and drive resolution of complex technical issues
•Experience with physical design methodologies (flow and tools development), chip floorplan, power/clock/reset distribution, DFT, place and route, timing closure, and packaging

Experience:10+ yearsSemiconductorsASICSoCGPU

Education:Master's

Skills:PythonPerlC++

Tech Stack:PythonPerlC++ASICFloorplanningDFTPlace and RouteTiming Closure

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

Loading job details...

Preparing the role view and application actions.

NVIDIA

1 month ago

Senior ASIC Floorplan Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Location: Santa Clara, Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Collaborate with product managers, chip architects, ASIC design, physical design, and packaging teams to craft chip floorplans that optimize cost/area, performance, and power for target markets
•Drive floorplan development and work with ASIC/Physical Design teams to identify and solve area, interconnect, timing, and floorplan improvement opportunities
•Develop AI workflows and productivity tools to improve infrastructure for optimizing chip area and speed of execution
•Identify key technical and product risks and work with engineering and management to implement risk mitigation strategies
•Communicate progress and options to align multiple multidisciplinary teams on floorplan decisions

Pay and Benefits

Salary: USD 196,000 - 310,500 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•MSEE/MSCE (or equivalent) with broad and deep experience in chip development
•10+ years of experience
•Experience with developing SOC, CPU, graphics, memory, and I/O sub-systems in the chip
•Ability to multi-task across simultaneous projects and drive resolution of complex technical issues
•Experience with physical design methodologies (flow and tools development), chip floorplan, power/clock/reset distribution, DFT, place and route, timing closure, and packaging

Experience:10+ yearsSemiconductorsASICSoCGPU

Education:Master's

Skills:PythonPerlC++

Tech Stack:PythonPerlC++ASICFloorplanningDFTPlace and RouteTiming Closure

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor