RTL Design Engineer

AMD
Bengaluru
Full timeINR 3,338,160 - 4,768,800 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsEducation: mastersSkills: ["Team player","Excellent communication skills","Analytical skills","Problem-solving skills","Willing to learn"]

Design and microarchitect data fabric IP RTL for Infinity Data Fabric, delivering new and existing features as it scales for server and data center systems. Write and optimize RTL in Verilog/SystemVerilog, create power management flows and architecture (including UPF), and run design quality checks (lint, CDC/RDC). Collaborate with architects, verification, and integration teams to resolve IP integration issues and achieve timing closure and low-power designs.

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FursaFursa
AMD
AMD
3 days ago

RTL Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Design and microarchitect data fabric IP RTL for Infinity Data Fabric, delivering new and existing features as it scales for server and data center systems. Write and optimize RTL in Verilog/SystemVerilog, create power management flows and architecture (including UPF), and run design quality checks (lint, CDC/RDC). Collaborate with architects, verification, and integration teams to resolve IP integration issues and achieve timing closure and low-power designs.
Location: Bengaluru
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Microarchitect and implement components of the Infinity Data Fabric.
  • •Develop RTL coding for data fabric components and features as the fabric scales for server and data center systems.
  • •Design power management flows and architecture for the fabric, including low power techniques with UPF.
  • •Collaborate with architects to understand new features to be implemented and with verification/integration teams to resolve inter-IP integration issues.
  • •Perform design flow quality checks (lint, CDC, RDC), drive timing closure, and optimize design area and logic depth.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •7+ years of working experience in ASIC design.
  • •Proficiency in Verilog/SystemVerilog RTL.
  • •Experience with the full IP design cycle, including requirements definition, architecture, and microarchitecture specification.
  • •Knowledge of ASIC design quality flows.
  • •Bachelors or Masters degree in computer engineering or electrical engineering.
Experience:7+ yearsASIC designRTLProcessor architectureDigital designVerification
Education:Master's in Computer engineering/Electrical Engineering
Skills:Team playerExcellent communication skillsAnalytical skillsProblem-solving skillsWilling to learn
Tech Stack:VerilogSystemVerilogUPFInfinity Data FabricData fabric IPLintCDCRDCSynthesisTiming constraintsLogic-depth reductionTiming closure

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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