Principal DFT Engineer (Silicon Engineering)

Develop and optimize DFT architectures for next-generation ASICs used in space and ground Starlink infrastructure. Lead ATPG tools and methodologies, including pattern generation for fault models, hierarchical test flows, and post-silicon testing support. Validate scan insertion readiness using RTL and physical DRC tools, integrate and verify DFT fabrics/IP, and debug gate-level simulations while automating test scripts and analyzing results.