Senior ASIC Design Verification Engineer

Cisco
San Jose
Workplace: OnsiteFull timeUSD 167,700 - 245,200 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsSkills: ["Clear communication","Collaboration","Partnership","Task management"]

Build and maintain ASIC design verification environments for block, cluster, and top-level components. Own end-to-end verification including simulation models, test planning, constrained/random testing, and coverage implementation for multi-chip/system scenarios and post-silicon bring-up. Drive verification coverage through code and functional coverage reviews, collaborate with hardware designers, architects, software teams, and vendors, and manage multiple concurrent tasks with clear communication.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cisco
Cisco
1 day ago

Senior ASIC Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Build and maintain ASIC design verification environments for block, cluster, and top-level components. Own end-to-end verification including simulation models, test planning, constrained/random testing, and coverage implementation for multi-chip/system scenarios and post-silicon bring-up. Drive verification coverage through code and functional coverage reviews, collaborate with hardware designers, architects, software teams, and vendors, and manage multiple concurrent tasks with clear communication.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Architect, develop, and maintain block, cluster, and top-level design verification environment infrastructure.
  • •Perform end-to-end verification of design blocks and top-level components.
  • •Develop simulation models, test plans, and run directed/random tests with coverage (code and functional).
  • •Ensure comprehensive verification coverage through coverage implementation and review.
  • •Collaborate with designers, architects, software teams, and vendors, and lead multiple concurrent tasks effectively.

Pay and Benefits

Salary: USD 167,700 - 245,200 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kPaid ParentalLong-term DisabilityLife InsurancePaid HolidaysPaid LeaveAnnual BonusEquity

Key Requirements

  • •Bachelor’s degree in Electrical or Computer engineering with 7+ years of ASIC-related experience, or Master’s with 4+ years, or PhD with 1+ year.
  • •Prior experience in SystemVerilog and UVM.
  • •Experience with ASIC design/verification processes, debugging, methodology, and verification tools.
  • •Experience verifying blocks, clusters, and/or full-chip level ASIC designs.
  • •Practical experience supporting comprehensive verification coverage through code and functional coverage implementation.
Experience:7+ yearsASICSemiconductorsPost-silicon bring-upNetworking
Education:
Skills:Clear communicationCollaborationPartnershipTask management
Tech Stack:System VerilogUVMLinuxCC++PythonPerlPCIeAXI

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
Glassdoor
Glassdoor: 4.0
WebsiteLinkedInGlassdoor