Lead Design Engineer
Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4-6 yearsEducation: high_schoolSkills: ["SystemVerilog","UVM","BFM","Scoreboards","Checks","Formal verification","DV","Verification planning","Testbench architecture"]Lead verification efforts for complex semiconductor/ASIC/SoC designs, defining verification strategy (UVM/SystemVerilog), designing scalable testbenches with BFMs, and guiding cross-functional teams to ensure high functional coverage and timely sign-off on verification milestones.
