Lead Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4-6 yearsEducation: high_schoolSkills: ["SystemVerilog","UVM","BFM","Scoreboards","Checks","Formal verification","DV","Verification planning","Testbench architecture"]

Lead verification efforts for complex semiconductor/ASIC/SoC designs, defining verification strategy (UVM/SystemVerilog), designing scalable testbenches with BFMs, and guiding cross-functional teams to ensure high functional coverage and timely sign-off on verification milestones.

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Cadence Design Systems
Cadence Design Systems
2 months ago

Lead Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Lead verification efforts for complex semiconductor/ASIC/SoC designs, defining verification strategy (UVM/SystemVerilog), designing scalable testbenches with BFMs, and guiding cross-functional teams to ensure high functional coverage and timely sign-off on verification milestones.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Define verification strategy and architecture for the project, selecting methodology, tools, and infrastructure.
  • •Design scalable verification environments including BFMs, monitors, scoreboards, and checkers.
  • •Identify critical features requiring rigorous testing and perform feature extraction from architectural specs.
  • •Lead execution and technical leadership by writing complex test cases, debugging root causes, and guiding junior engineers.
  • •Oversee constrained-random stimulus generation and formal verification to expand design space and prove properties.

Key Requirements

  • •BE/B.Tech or M.Tech/MS in Electronics, VLSI, or related field
  • •4–6 years of hands-on DV experience in semiconductor/ASIC/SoC
  • •experience with verification methodologies (UVM/SystemVerilog) and testbench architecture
  • •ability to lead root-cause analysis and debugging of complex design bugs
  • •experience with constrained-random testing and formal verification
Experience:4-6 yearsSemiconductorASICSoCVLSI
Education:High School
Skills:SystemVerilogUVMBFMScoreboardsChecksFormal verificationDVVerification planningTestbench architecture
Tech Stack:SystemVerilogUVMBFMScoreboardRandom testingFormal verification

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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