Lead Product Engineer - Design Verification (MM/VIP)

Cadence Design Systems
Ahmedabad, Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4-8 yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","Memory protocols","DDR5","GDDR6","DFI"]

Lead Product Engineer responsible for driving development and verification of Cadence Memory Verification IP (VIP) in the MM VIP family, focusing on SDRAM/DDR5, GDDR6, DFI and related protocols. Works with cross-functional teams, provides training and collaterals, translates customer requirements into technical specs, and supports pre-sales activities while collaborating across geographies with about 20% travel.

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Cadence Design Systems
Cadence Design Systems
7 months ago

Lead Product Engineer - Design Verification (MM/VIP)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 12 hours agoStatus: Live

Job Summary

Lead Product Engineer responsible for driving development and verification of Cadence Memory Verification IP (VIP) in the MM VIP family, focusing on SDRAM/DDR5, GDDR6, DFI and related protocols. Works with cross-functional teams, provides training and collaterals, translates customer requirements into technical specs, and supports pre-sales activities while collaborating across geographies with about 20% travel.
Location: Ahmedabad, Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Leads projects with high resource, risk and/or complexity.
  • •Develops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity.
  • •Continually evaluates technology effectiveness/data interoperability of complex systems.
  • •Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products.
  • •Communicates highly complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view.
Travel: Medium travel

Key Requirements

  • •4–8 years of experience with Design and Verification.
  • •Experience with developing verification environments using SystemVerilog.
  • •Working knowledge and experience with the UVM methodology.
  • •Familiarity with Memory protocols is a must; knowledge of the DFI protocol is a plus.
  • •Excellent problem-solving and debugging skills, able to analyze complex situations and data.
Experience:4-8 yearsMemory verificationSemiconductorsVerification IP
Education:Bachelor's
Skills:SystemVerilogUVMMemory protocolsDDR5GDDR6DFI
Tech Stack:SystemVerilogUVMDDR5GDDR6DFIMemory Protocols

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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