DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ years

Cisco
Bengaluru, Chennai, Hyderabad
Workplace: HybridFull timeFunction: Administration & Executive AssistanceExperience: 10-12 yearsEducation: mastersSkills: ["Verbal communication","Problem-solving","Debugging","Cross-functional collaboration","Independent ownership"]

Own implementation of Hardware Design-for-Test (DFT) features that enable ATE, in-system test, debug, and diagnostics. Develop innovative DFT IP and drive testability integration with RTL so test logic is integrated and validated across implementation and post-silicon flows. Partner with design, design-verification, and PD teams to create reusable test and debug strategies for new silicon models and physical design needs. Debug complex systems with minimal mentorship.

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FursaFursa
Cisco
Cisco
3 days ago

DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ years

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Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live

Job Summary

Own implementation of Hardware Design-for-Test (DFT) features that enable ATE, in-system test, debug, and diagnostics. Develop innovative DFT IP and drive testability integration with RTL so test logic is integrated and validated across implementation and post-silicon flows. Partner with design, design-verification, and PD teams to create reusable test and debug strategies for new silicon models and physical design needs. Debug complex systems with minimal mentorship.
Location: Bengaluru, Chennai, Hyderabad
Workplace: Hybrid
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Implement Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics needs.
  • •Develop innovative DFT IP and contribute to full chip design integration with testability features coordinated in the RTL.
  • •Work with design, design-verification, and PD teams to integrate and validate test logic across implementation phases and post-silicon validation flows.
  • •Participate in creating innovative DFT and physical design aspects for new silicon device models, bare die and stacked die, and reusable test/debug strategies.
  • •Craft solutions and debug complex issues with minimal mentorship.

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical or Computer Engineering with 10–12 years of experience.
  • •Knowledge of the latest innovative trends in DFT, test, and silicon engineering.
  • •Experience with JTAG protocols plus scan and BIST architectures, including memory BIST and boundary scan.
  • •Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime.
  • •Verification experience including SystemVerilog logic equivalency checking and validating test timing; experience with gate-level simulation and debugging with VCS and other simulators.
Experience:10-12 yearsDFTSemiconductorHardwareEDASilicon engineering
Education:Master's in Electrical or Computer Engineering
Skills:Verbal communicationProblem-solvingDebuggingCross-functional collaborationIndependent ownership
Tech Stack:DFTATEJTAGScanBISTMemory BISTBoundary scanATPGTestMaxTetramaxTessentPrimeTimeSystemVerilogRTLP1687EDA toolsGate-level simulationVCSTclPython

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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