Physical Design Engineer - Physical Verification - Singapore

ByteDance
Singapore
Full timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Debugging","Technical problem solving","Cross-vendor collaboration","Issue tracking"]

Own and drive physical verification (PV) signoff for advanced-node ASIC/SoC designs, including DRC/LVS/ERC/ANT, fill program, ESD and reliability checks, and GDS scramble and package-related verification. Manage the PV flow from early PDK test enablement through final tapeout, including methodology development, flow bring-up, debugging, and signoff closure. Partner with Foundry and EDA vendors on rule-deck bring-up, issue resolution, and PV result correlation.

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FursaFursa
ByteDance
ByteDance
14 hours ago

Physical Design Engineer - Physical Verification - Singapore

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Source: Company careers pageValidated by: Fursa AI
Last checked: 14 hours agoStatus: Live

Job Summary

Own and drive physical verification (PV) signoff for advanced-node ASIC/SoC designs, including DRC/LVS/ERC/ANT, fill program, ESD and reliability checks, and GDS scramble and package-related verification. Manage the PV flow from early PDK test enablement through final tapeout, including methodology development, flow bring-up, debugging, and signoff closure. Partner with Foundry and EDA vendors on rule-deck bring-up, issue resolution, and PV result correlation.
Location: Singapore
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Own and drive physical verification (PV) signoff for advanced-node ASIC/SoC designs, including DRC/LVS/ERC/ANT, fill program, ESD PERC/reliability checks, GDS scramble, and advanced package-related verification.
  • •Own the complete PV flow from early PDK test/enablement through final tapeout, including PV methodology development, flow bring-up, debugging, and signoff closure.
  • •Drive early PDK and rule-deck bring-up and validation; for immature PDKs/decks, analyze results, identify root causes, develop focused test cases, and work with Foundry/EDA vendors to reach closure.
  • •Perform in-depth PV result analysis and debugging, including hierarchical/flat monitoring, IP verification and SoC integration, regression analysis across rule-deck/PDK versions, and PV-PR correlation.
  • •Serve as the technical interface with Foundry/PDK teams and EDA vendors by reporting/tracking issues, preparing test cases, discussing rule interpretation, and validating rule-deck fixes; develop and maintain PV signoff methodology.

Key Requirements

  • •BS degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
  • •5+ years of experience in physical verification (DRC/LVS/ERC) for ASIC/SoC designs.
  • •Hands-on experience with industry-standard PV tools such as Mentor Calibre and Synopsys IC Validator.
  • •Experience running PV signoff flow from PDK enablement through tapeout.
  • •Experience working with Foundry and EDA vendors on rule-deck bring-up and issue resolution.
Experience:5+ yearsASICSoCEDAChip design
Education:Bachelor's in Electrical Engineering, Computer Engineering
Skills:DebuggingTechnical problem solvingCross-vendor collaborationIssue tracking
Tech Stack:DRCLVSERCANTGDS scrambleMentor CalibreSynopsys IC ValidatorPDKRule decksESD PERCGDSTapeout

Company Brief

ByteDance
Develops consumer internet and content platforms, including TikTok and other apps for short-form video, news, and entertainment. It also builds advertising, commerce, and creator tools that connect audiences, brands, and publishers across global markets.
Industry: Digital Media
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Established Company
Headquarters: Beijing, China
Founded: 2012
WebsiteLinkedIn