STA/Constraints Engineer

Develop FullChip timing constraints and drive timing closure for SOC and subsystem integration. Partner with SOC Architecture and cross-functional teams across physical design, timing analysis, synthesis, physical verification, and power signoff, while mentoring design engineers. Build and validate SDC/STA workflows, analyze timing margins and CDC, and support FCT closure. Collaborate with CAD/EDA vendors and improve netlist quality through lint/cdc checks and lower-power implementation.