STA/Constraints Engineer

AMD
Santa Clara
Workplace: HybridFull timeFunction: Data Science & Machine LearningEducation: bachelorsSkills: ["Presentation","Communication","Inter-communication","Task scheduling","Time management"]

Develop FullChip timing constraints and drive timing closure for SOC and subsystem integration. Partner with SOC Architecture and cross-functional teams across physical design, timing analysis, synthesis, physical verification, and power signoff, while mentoring design engineers. Build and validate SDC/STA workflows, analyze timing margins and CDC, and support FCT closure. Collaborate with CAD/EDA vendors and improve netlist quality through lint/cdc checks and lower-power implementation.

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FursaFursa
AMD
AMD
1 month ago

STA/Constraints Engineer

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Last checked: 2 hours agoStatus: Live

Job Summary

Develop FullChip timing constraints and drive timing closure for SOC and subsystem integration. Partner with SOC Architecture and cross-functional teams across physical design, timing analysis, synthesis, physical verification, and power signoff, while mentoring design engineers. Build and validate SDC/STA workflows, analyze timing margins and CDC, and support FCT closure. Collaborate with CAD/EDA vendors and improve netlist quality through lint/cdc checks and lower-power implementation.
Location: Santa Clara
Workplace: Hybrid
Employment Type: Full time
Job Function: Data Science & Machine Learning

Key Responsibilities

  • •Develop FullChip constraints and own end-to-end timing closure delivery for SOC and subsystem integration.
  • •Set up clock design requirements in SDC and partner with SOC Architecture/SOC clocks & STA for statistical timing target goals.
  • •Analyze timing margins (LVF/SSTA/variations) on latest tech nodes and collaborate with timing methodology teams on current and future projects.
  • •Deliver FCT closure by understanding design requirements, timelines, and project milestones.
  • •Drive SDC/STA development, shift-left timing closure, CDC/clock domain crossing, and support cdc/lint, lower power implementation, and netlist quality checks.

Key Requirements

  • •Industry experience in STA, constraints, timing signoff, and physical design.
  • •Expert user of SNPS PT/GCA (must) and ICC2/FC (desired).
  • •Knowledge of DFT timing concepts including MBIST, top-level clock implementation, place and route (floorplanning/placement), CTS, and routing.
  • •Experience with Perl/TCL/Shell/Python scripting and Verilog RTL design.
  • •Bachelor/Master’s degree in Micro Electronics or Integrated Circuit Science (or related field preferred).
Experience:ASICPhysical design
Education:Bachelor's in Micro Electronics / Integrated Circuit Science
Skills:PresentationCommunicationInter-communicationTask schedulingTime management
Tech Stack:SDCSTA (Static Timing)SNPS PT/GCAICC2/FCLVFSSTALVF/SSTASDC developmentCDCFCTTiming signoffCcts (CTS)Place and RouteFloorplanningRoutingPerlTCLShellPythonVerilog

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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