Design Verification Lead

Lead design verification efforts for next-generation PCIe and CXL FPGA/ASIC IP, partnering with architecture, IP design, physical design, firmware, and product engineering teams. Own end-to-end verification planning, including feature interaction coverage and system-level use cases. Build UVM-based verification environments (monitors, scoreboards, checkers), develop directed and constrained-random tests, debug regressions, and drive verification automation and methodology improvements, including AI-assisted tooling adoption.