Design Verification Lead

AMD
San Jose
Workplace: HybridFull timeUSD 175,000 - 250,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: bachelorsSkills: ["Technical leadership","Mentoring","Communication","Collaboration","Analytical skills"]

Lead design verification efforts for next-generation PCIe and CXL FPGA/ASIC IP, partnering with architecture, IP design, physical design, firmware, and product engineering teams. Own end-to-end verification planning, including feature interaction coverage and system-level use cases. Build UVM-based verification environments (monitors, scoreboards, checkers), develop directed and constrained-random tests, debug regressions, and drive verification automation and methodology improvements, including AI-assisted tooling adoption.

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FursaFursa
AMD
AMD
1 month ago

Design Verification Lead

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live

Job Summary

Lead design verification efforts for next-generation PCIe and CXL FPGA/ASIC IP, partnering with architecture, IP design, physical design, firmware, and product engineering teams. Own end-to-end verification planning, including feature interaction coverage and system-level use cases. Build UVM-based verification environments (monitors, scoreboards, checkers), develop directed and constrained-random tests, debug regressions, and drive verification automation and methodology improvements, including AI-assisted tooling adoption.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Collaborate with architects, hardware designers, and firmware teams to define and verify PCIe, CXL, and high-speed connectivity features.
  • •Develop comprehensive verification plans covering feature interactions, hardware/software integration, performance requirements, and system-level use cases.
  • •Design and implement UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components.
  • •Develop directed and constrained-random tests, run regressions, and debug failures to ensure high functional coverage and design quality.
  • •Drive verification automation and methodology improvements, including adoption of AI-assisted tools to increase efficiency and productivity.

Pay and Benefits

Salary: USD 175,000 - 250,000 annually

Key Requirements

  • •Minimum 10 years of design verification experience using UVM methodology.
  • •Strong expertise in SystemVerilog and Verilog, including object-oriented programming and UVM-based verification environments.
  • •ASIC/IP verification experience using the UVM methodology to build verification environments and components.
  • •Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
  • •Proficiency in scripting and automation using Python, Perl, or similar languages.
Experience:10+ yearsASIC/FPGAHigh-speed protocols
Education:Bachelor's in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Skills:Technical leadershipMentoringCommunicationCollaborationAnalytical skills
Tech Stack:FPGAASICPCIeCXLEthernetUVMSystemVerilogVerilogPythonPerlHLSAI

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn