1 week ago

Principal Chip Lead, Silicon Co-Design Group

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 22 hours agoStatus: Live

Job Summary

Serve as the single technical point of contact for a silicon program, partnering with design, validation, software, and manufacturing to keep the technical narrative clear and on track. Co-lead chip-to-system feature integration, resolve the hardest multi-functional bugs across areas like HBM, power/thermal, high-speed I/O, and packaging, and steward the qualification playbook. Present decision-ready risks and mitigations to executives while mentoring other Chip Leads.

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Act as the single technical point of contact for multi-functional decisions, issues, and trade-offs.
•Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution.
•Resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure across areas such as HBM, power and thermal, high-speed I/O, and packaging.
•Steward the qualification playbook, guiding mitigations when it does not fit and capturing lessons as reusable methodology.
•Shape the program’s technical narrative by surfacing key risks, trade-offs, and mitigations as decision-ready options for executive leadership; lead Critical Debug and SCG Technical Execution forums.

Pay and Benefits

Salary: USD 232,000 - 368,000 annually

Equity and Bonus:Equity

Key Requirements

•BS or MS (or equivalent) in Electrical or Computer Engineering.
•Over a decade of proven track record in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company, including work on multiple shipped silicon products.
•15+ years of experience.
•Strong end-to-end understanding of SoC and ASIC architecture, with recognized expertise in at least one subsystem such as HBM, SerDes, power and thermal, or packaging.
•Demonstrated examples of silicon-level impact, including turning ambiguous, multi-team failure modes into root-cause closure with reusable workarounds and write-ups.

Experience:15+ yearsSemiconductorSoCASICPost-silicon bring-upValidationSystem integration

Education:Bachelor's in Electrical or Computer Engineering

Skills:Technical leadershipCross-functional collaborationProblem-solvingMentorshipExecutive communication

Tech Stack:SoCASICHBMSerDesPower and thermalHigh-speed I/OPackagingPost-silicon bring-upValidationSystem integrationQualification playbook

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

Loading job details...

Preparing the role view and application actions.

NVIDIA

1 week ago

Principal Chip Lead, Silicon Co-Design Group

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 22 hours agoStatus: Live

Job Summary

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Act as the single technical point of contact for multi-functional decisions, issues, and trade-offs.
•Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution.
•Resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure across areas such as HBM, power and thermal, high-speed I/O, and packaging.
•Steward the qualification playbook, guiding mitigations when it does not fit and capturing lessons as reusable methodology.
•Shape the program’s technical narrative by surfacing key risks, trade-offs, and mitigations as decision-ready options for executive leadership; lead Critical Debug and SCG Technical Execution forums.

Pay and Benefits

Salary: USD 232,000 - 368,000 annually

Equity and Bonus:Equity

Key Requirements

•BS or MS (or equivalent) in Electrical or Computer Engineering.
•Over a decade of proven track record in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company, including work on multiple shipped silicon products.
•15+ years of experience.
•Strong end-to-end understanding of SoC and ASIC architecture, with recognized expertise in at least one subsystem such as HBM, SerDes, power and thermal, or packaging.
•Demonstrated examples of silicon-level impact, including turning ambiguous, multi-team failure modes into root-cause closure with reusable workarounds and write-ups.

Experience:15+ yearsSemiconductorSoCASICPost-silicon bring-upValidationSystem integration

Education:Bachelor's in Electrical or Computer Engineering

Skills:Technical leadershipCross-functional collaborationProblem-solvingMentorshipExecutive communication

Tech Stack:SoCASICHBMSerDesPower and thermalHigh-speed I/OPackagingPost-silicon bring-upValidationSystem integrationQualification playbook

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor