NVIDIA

1 day ago

Analog Mask Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Own IC mask layout for cutting-edge, high-performance analog and mixed-signal CMOS blocks in advanced foundry process nodes. Drive physical verification (DRC, LVS, density analysis) and tape-out checks, resolve complex layout issues, and optimize for performance, area, and manufacturability. Lead custom layout of key analog IP (op-amps, bandgaps, ADCs/DACs, LDOs, regulators) while ensuring matching/symmetry/parasitic sensitivity and collaborating across multi-functional teams.

Location: Bengaluru

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Execute IC layout for high-performance, high-speed CMOS integrated circuits in advanced foundry process nodes.
•Optimize physical verification activities including DRC, LVS, density analysis, and tape-out checks.
•Drive identification and resolution of complex physical design issues, mentoring junior engineers in established methodologies.
•Develop analog layouts and lead optimization efforts for performance, area, and manufacturability.
•Lead full custom layout of analog/mixed-signal blocks (e.g., op-amps, bandgaps, ADCs, DACs, LDOs, voltage regulators) while ensuring design quality requirements.

Key Requirements

•2+ years of experience in high-performance analog layout in advanced CMOS process.
•BE/M-Tech in Electrical & Electronics or equivalent experience.
•Thorough knowledge of industry-standard EDA tools for Cadence.
•Experience with layout of high-performance analog blocks such as current mirrors, sense amps, and bandgaps.
•Knowledge of analog design and layout guidelines including high-speed IO and techniques like common centroid and signal shielding.

Experience:2+ yearsAnalog layoutCMOSFoundry design

Education:Bachelor's in Electrical & Electronics

Skills:MentoringTeamworkResource management

Tech Stack:Cadence

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

Loading job details...

Preparing the role view and application actions.

NVIDIA

1 day ago

Analog Mask Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Execute IC layout for high-performance, high-speed CMOS integrated circuits in advanced foundry process nodes.
•Optimize physical verification activities including DRC, LVS, density analysis, and tape-out checks.
•Drive identification and resolution of complex physical design issues, mentoring junior engineers in established methodologies.
•Develop analog layouts and lead optimization efforts for performance, area, and manufacturability.
•Lead full custom layout of analog/mixed-signal blocks (e.g., op-amps, bandgaps, ADCs, DACs, LDOs, voltage regulators) while ensuring design quality requirements.

Key Requirements

•2+ years of experience in high-performance analog layout in advanced CMOS process.
•BE/M-Tech in Electrical & Electronics or equivalent experience.
•Thorough knowledge of industry-standard EDA tools for Cadence.
•Experience with layout of high-performance analog blocks such as current mirrors, sense amps, and bandgaps.
•Knowledge of analog design and layout guidelines including high-speed IO and techniques like common centroid and signal shielding.

Experience:2+ yearsAnalog layoutCMOSFoundry design

Education:Bachelor's in Electrical & Electronics

Skills:MentoringTeamworkResource management

Tech Stack:Cadence

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor