2 months ago

RTL2GDS, Senior Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Lead senior design engineering efforts to enable RTL-to-GDSII flow for Cadence front-end tools, supporting tapeouts for ASIC blocks across multiple technology nodes. Own block implementation and signoff-focused projects, articulate design methodologies, and benchmark complex CPU/GPU/DSP cores for automotive, wireless and mobile customers. Frequent collaboration with regional customers and Cadence field engineers to differentiate Cadence solutions.

Location: Austin, San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Lead and manage front-end design projects, including RTL-to-GDSII delivery and tapeouts for ASIC blocks across multiple technology nodes.
•Benchmark and evaluate Cadence tools against competitor solutions, driving technology differentiation and best practices back into product development.
•Create and deliver technical presentations and product demonstrations to customers, articulating design methodologies and tool capabilities.
•Support regional customers with substantial involvement (50%+), ensuring successful design implementations and customer satisfaction.
•Collaborate with sales engineers and field teams to understand customer needs and translate them into concrete design solutions.

Key Requirements

•BS degree in a technical field with 7+ years of experience
•ASIC design experience using Verilog
•Deep Cadence or Synopsys place-and-route tool knowledge (Physical Synthesis, PnR, CTS, STA)
•Experience with low-power and multi-voltage design techniques
•RTL-to-GDS implementation flows using Encounter Digital Implementation Platform

Experience:7+ yearsSemiconductorEDAASICChip design

Education:Bachelor's

Skills:CommunicationPresentationProblem-solvingCollaboration

Tech Stack:VerilogGenusDFTSynthesisPhysical SynthesisP&RCTSSTAGDSIIEncounterDigital ImplementationRTLGDSII delivery

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

2 months ago

RTL2GDS, Senior Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Austin, San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Lead and manage front-end design projects, including RTL-to-GDSII delivery and tapeouts for ASIC blocks across multiple technology nodes.
•Benchmark and evaluate Cadence tools against competitor solutions, driving technology differentiation and best practices back into product development.
•Create and deliver technical presentations and product demonstrations to customers, articulating design methodologies and tool capabilities.
•Support regional customers with substantial involvement (50%+), ensuring successful design implementations and customer satisfaction.
•Collaborate with sales engineers and field teams to understand customer needs and translate them into concrete design solutions.

Key Requirements

•BS degree in a technical field with 7+ years of experience
•ASIC design experience using Verilog
•Deep Cadence or Synopsys place-and-route tool knowledge (Physical Synthesis, PnR, CTS, STA)
•Experience with low-power and multi-voltage design techniques
•RTL-to-GDS implementation flows using Encounter Digital Implementation Platform

Experience:7+ yearsSemiconductorEDAASICChip design

Education:Bachelor's

Skills:CommunicationPresentationProblem-solvingCollaboration

Tech Stack:VerilogGenusDFTSynthesisPhysical SynthesisP&RCTSSTAGDSIIEncounterDigital ImplementationRTLGDSII delivery

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor