ASIC Implementation Engineer PD

Own ASIC top-level floorplanning and partitioning, including clock tree delivery and top-level partition implementation, for next-generation AI and PCIe switch products. Resolve physical design issues across chip integration and assembly, coordinating closely with package teams on I/O and bump planning. Improve floorplan methodologies using industry and internal tools, evaluate vendors and IP for design specification fit, and support RTL-to-silicon tape-out at advanced nodes.