ASIC Implementation Engineer PD

Broadcom
San Jose
Workplace: OnsiteFull timeUSD 121,900 - 195,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 6-8 yearsEducation: bachelorsSkills: ["Cross-functional collaboration","Problem-solving","Technical evaluation","Methodology development","Technical assessment"]

Own ASIC top-level floorplanning and partitioning, including clock tree delivery and top-level partition implementation, for next-generation AI and PCIe switch products. Resolve physical design issues across chip integration and assembly, coordinating closely with package teams on I/O and bump planning. Improve floorplan methodologies using industry and internal tools, evaluate vendors and IP for design specification fit, and support RTL-to-silicon tape-out at advanced nodes.

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FursaFursa
Broadcom
Broadcom
1 month ago

ASIC Implementation Engineer PD

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Source: Company careers pageValidated by: Fursa AI
Last checked: 12 days agoStatus: Live

Job Summary

Own ASIC top-level floorplanning and partitioning, including clock tree delivery and top-level partition implementation, for next-generation AI and PCIe switch products. Resolve physical design issues across chip integration and assembly, coordinating closely with package teams on I/O and bump planning. Improve floorplan methodologies using industry and internal tools, evaluate vendors and IP for design specification fit, and support RTL-to-silicon tape-out at advanced nodes.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Own chip floor planning, partition creation, clock tree delivery, and top-level partition implementation.
  • •Resolve physical design issues related to chip integration and assembly.
  • •Coordinate cross-functionally with package teams on top-level floorplanning, I/O, and bump planning.
  • •Develop and improve floorplan implementation methodologies using industry and internal tools.
  • •Evaluate vendors and IP, providing recommendations and assessments to meet design specifications.

Pay and Benefits

Salary: USD 121,900 - 195,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEquityEsppPaid Leave

Key Requirements

  • •Bachelor’s degree in Electrical Engineering with 8+ years of experience in top-level floorplanning (die size estimate, partitioning, clocking, pin planning), or a Master’s degree with 6+ years.
  • •Experience with ASIC physical design across RTL-to-silicon tape-out.
  • •Experience with technologies such as switch fabric, arbiter, high-speed DDR, SerDes, HBM, D2D I/O, and chiplets.
  • •Experience resolving chip-level DRC/LVS/EMIR issues for advanced nodes.
  • •Experience with bump planning, RDL implementation, multi-voltage domain designs, and scripting languages like Python, Tcl, or Perl (plus relevant EDA tools).
Experience:6-8 yearsSemiconductorASICPhysical designEDA
Education:Bachelor's in Electrical Engineering
Skills:Cross-functional collaborationProblem-solvingTechnical evaluationMethodology developmentTechnical assessment
Tech Stack:ASICPhysical designRTLSilicon tape-outFloorplanningPartitioningClock treeI/O planningBump planningRDL implementationDRCLVSEMIRStructured clocksPower grid designHierarchical floorplanningCustom routesSwitch fabricArbiterDDR

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn