Host and Network IO FPGA Engineer

Cerebras
Sunnyvale, Toronto
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 5+ yearsEducation: phdSkills: ["Cross-functional communication","Debugging","Collaboration","Technical leadership"]

Own the in-chassis IO subsystem for Cerebras’ AI hardware, spanning RoCE v2 network interfaces with a custom RDMA protocol implementation, a programmable switching fabric, and proprietary serial IO. Lead chassis-to-wafer IO architecture and next-gen FPGA RTL/bitstream development for deployment in large inference clusters. Optimize bandwidth and latency, drive network performance debug, and coordinate with DV, board, cluster, and embedded software teams to integrate hardware and software for improved network IO.

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FursaFursa
Cerebras
Cerebras
1 day ago

Host and Network IO FPGA Engineer

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Last checked: 4 hours agoStatus: Live

Job Summary

Own the in-chassis IO subsystem for Cerebras’ AI hardware, spanning RoCE v2 network interfaces with a custom RDMA protocol implementation, a programmable switching fabric, and proprietary serial IO. Lead chassis-to-wafer IO architecture and next-gen FPGA RTL/bitstream development for deployment in large inference clusters. Optimize bandwidth and latency, drive network performance debug, and coordinate with DV, board, cluster, and embedded software teams to integrate hardware and software for improved network IO.
Location: Sunnyvale, Toronto
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Lead full chassis-to-wafer IO architecture and design.
  • •Improve current RTL, implement next-gen FPGA designs, and define future IO architectures.
  • •Produce production-ready FPGA bitstreams for deployment into large clusters running customer inference services.
  • •Optimize bandwidth/latency across FPGA datapaths and all IO interfaces, and drive network performance debug of large AI clusters.
  • •Lead cross-functional technical projects integrating diverse software and hardware components to deliver improved network IO solutions.

Key Requirements

  • •5+ years of industry experience generating production FPGA solutions, OR a Master’s/PhD in Computer or Electrical Engineering with 3+ years industry experience.
  • •Proficiency in Verilog development in a Git-based repository.
  • •Strong FPGA placement & routing, timing closure, simulation, and debug using FPGA tool/workflow environments.
  • •Familiarity with network protocols including TCP and RoCE, and network debugging tools such as Wireshark.
  • •Knowledge of network switch environments (e.g., Arista, Juniper) or willingness to learn.
Experience:5+ yearsAIFPGANetworking
Education:PhD / Doctorate in Computer or Electrical Engineering
Skills:Cross-functional communicationDebuggingCollaborationTechnical leadership
Tech Stack:FPGAVerilogGitRDMARoCE v2TCPWiresharkAristaJuniper

Company Brief

Cerebras
Designs and builds wafer-scale AI accelerators and systems for large-scale deep learning workloads, delivering specialized hardware and software to accelerate model training and inference for enterprises and research institutions.
Industry: Hardware Devices
Company Size: Large (251 to 1,000 employees)
Growth: Scaleup
Headquarters: Sunnyvale, United States
Founded: 2016
WebsiteLinkedIn