Lead Product Validation Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 4-6 yearsEducation: mastersSkills: ["Written communication","Verbal communication","Presentation skills","Communication","Teamwork"]

Lead product validation for IP/SoC platforms by building and running testbenches, creating tests, and driving verification activities through debugging and coverage closure. You’ll resolve simulation failures and protocol issues, collaborate with design, architecture, and validation teams, and support regression, reviews, and verification sign-off. The role requires strong SystemVerilog/UVM and hands-on protocol and SoC fundamentals, plus scripting and VHDL experience.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
1 day ago

Lead Product Validation Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 2 years ago

Job Summary

Lead product validation for IP/SoC platforms by building and running testbenches, creating tests, and driving verification activities through debugging and coverage closure. You’ll resolve simulation failures and protocol issues, collaborate with design, architecture, and validation teams, and support regression, reviews, and verification sign-off. The role requires strong SystemVerilog/UVM and hands-on protocol and SoC fundamentals, plus scripting and VHDL experience.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Develop testbenches, create tests, and execute verification.
  • •Debug simulation failures and protocol issues.
  • •Drive functional, code, and assertion coverage closure.
  • •Collaborate with design, architecture, and validation teams to support verification readiness.
  • •Support regression, reviews, and verification sign-off.

Key Requirements

  • •4-6 years of experience in IP / SoC Verification.
  • •Strong hands-on experience with SystemVerilog and UVM.
  • •Experience with high-speed protocols and a good understanding of SoC fundamentals.
  • •Strong debugging and problem-solving skills with coverage closure (functional, code, and assertion).
  • •Hands-on experience with VHDL design and scripting skills (Python/Perl/Shell).
Experience:4-6 yearsIP/SoC verificationElectronics
Education:Master's in Electrical/Electronics/Computer Engineering
Skills:Written communicationVerbal communicationPresentation skillsCommunicationTeamwork
Tech Stack:SystemVerilogUVMVHDLPythonPerlShell

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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