Design Verification Lead

Neurophos
Austin, Sunnyvale
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8-15 yearsSkills: ["Leadership","Collaboration","Testbench optimization","Coverage analysis","Communication"]

Own design verification methodology and testbench architecture for complex compute ASICs and GPU-class platforms, with a strong emphasis on AI-driven flows. Build verification plans across module simulation, SoC integration, interface checks, and top-level IO. Integrate third-party VIP, run gate-level simulation with SDF timing for tapeout closure, and extend an FPGA-based verification harness. Stand up cloud-hosted emulation and use AI tooling to generate and iterate testbenches and assertions while leading the verification team.

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FursaFursa
Neurophos
Neurophos
1 day ago

Design Verification Lead

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Last checked: 11 hours agoStatus: Live

Job Summary

Own design verification methodology and testbench architecture for complex compute ASICs and GPU-class platforms, with a strong emphasis on AI-driven flows. Build verification plans across module simulation, SoC integration, interface checks, and top-level IO. Integrate third-party VIP, run gate-level simulation with SDF timing for tapeout closure, and extend an FPGA-based verification harness. Stand up cloud-hosted emulation and use AI tooling to generate and iterate testbenches and assertions while leading the verification team.
Location: Austin, Sunnyvale
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Own verification methodology and testbench architecture built on UVM with emphasis on AI-driven flows.
  • •Build the verification plan across module-level simulation, SoC integration, interface checks, and top-level IO.
  • •Specify, evaluate, and integrate third-party VIP, and run gate-level simulation with SDF-annotated timing for tapeout closure.
  • •Extend the FPGA-based verification harness so modules can be exercised with real code and stand up emulation with provisioning/execution on cloud-hosted infrastructure.
  • •Use AI tooling to generate and iterate testbenches and assertions based on coverage feedback, and build/lead the verification team in partnership with adjacent design groups.

Pay and Benefits

Perks:Health InsurancePaid Leave401kEquityDentalVisionLife InsuranceHsa

Key Requirements

  • •8 to 15 years in design verification, including leading verification through tapeout on a GPU-class or complex compute ASIC.
  • •Deep expertise in UVM and SystemVerilog, including testbench architecture ownership, formal verification, coverage analysis, and CI/CD methodology.
  • •Experience with gate-level simulation, understanding its cost to visibility and its place in the tapeout schedule.
  • •Verification experience on chips with many independently developed blocks and analog components, including integration of analog models.
  • •Comfort standing up an end-to-end verification environment, including emulation infrastructure.
Experience:8-15 yearsASIC verificationGPU-class computeAI hardwareEmulationFPGA-based verification
Skills:LeadershipCollaborationTestbench optimizationCoverage analysisCommunication
Tech Stack:UVMSystemVerilogFormal verificationCoverage analysisCI/CDGate-level simulationSDFFPGAEmulationCloud-hosted infrastructureAI toolingTestbench generationAssertionsPalladiumWREALAnalog modelsFPGA-based verificationCadence toolchainSilicon photonicsOptical component verification

Company Brief

Neurophos
Develops metamaterial-based photonic optical processing units (OPUs) to deliver high-performance, energy-efficient AI inference chips for datacenters, aiming to scale photonic compute to exaflop levels.
Industry: Deep Tech
Company Size: Small (11 to 50 employees)
Growth: Growth Stage Startup
Funding: Series A
Headquarters: Austin, United States
Founded: 2020
WebsiteLinkedIn