Physical Design Engineer

Broadcom
Pune
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10-12 yearsEducation: mastersSkills: ["Cross-functional collaboration","Independent problem solving","Debugging","Stakeholder communication","Attention to detail"]

Apply Broadcom’s design methodology to deliver right-first-time silicon by owning static timing analysis and signoff readiness for block and full-chip designs. Develop and validate timing constraints, perform setup/hold and variation-aware analysis (OCV/AOCV/POCV, derates, MMMC), and debug violations with Synthesis, CTS, Physical Design, and Design teams. Drive ECO-based timing optimizations through pre- and post-layout signoff and report closure status to stakeholders.

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FursaFursa
Broadcom
Broadcom
3 weeks ago

Physical Design Engineer

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Last checked: 4 hours agoStatus: Live

Job Summary

Apply Broadcom’s design methodology to deliver right-first-time silicon by owning static timing analysis and signoff readiness for block and full-chip designs. Develop and validate timing constraints, perform setup/hold and variation-aware analysis (OCV/AOCV/POCV, derates, MMMC), and debug violations with Synthesis, CTS, Physical Design, and Design teams. Drive ECO-based timing optimizations through pre- and post-layout signoff and report closure status to stakeholders.
Location: Pune
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
  • •Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
  • •Partner with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
  • •Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
  • •Drive timing closure through ECO implementation and timing optimization, including variation (PVT) impact analysis and timing signoff support.

Key Requirements

  • •MSEE/MSCS with 10+ years, or BSEE/BSCS with 12+ years experience in static timing analysis (STA) and timing closure for block and/or full-chip designs.
  • •Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
  • •Hands-on experience with setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
  • •Good understanding of clock tree fundamentals including uncertainty, latency, skew, and jitter.
  • •Experience developing/debugging timing constraints (SDC, timing exceptions, false paths, multicycle paths) and using STA tools like Synopsys PrimeTime or Cadence Tempus.
Experience:10-12 yearsSemiconductor designStatic timing analysisTiming closure
Education:Master's
Skills:Cross-functional collaborationIndependent problem solvingDebuggingStakeholder communicationAttention to detail
Tech Stack:Static Timing Analysis (STA)Setup/hold analysisOCVAOCVPOCVDeratesMMMCClock treeClock uncertaintyLatencySkewJitterSDCTiming exceptionsFalse pathsMulticycle pathsECOSynopsys PrimeTimeCadence TempusTcl

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn