IC design Engineer

Own block-level and full-chip static (IR) and dynamic (IVD) sign-off, including power estimation for vector and vectorless workloads. Provide signal/power EM sign-off at block and full-chip level, support custom power grid implementation and PDN system-level analysis across board, package, interposer, and die. Collaborate with SoC and packaging teams on bump assignment and routing optimization, and perform vectorless/vectors/mixed-mode dynamic analysis and PG grid resistance checks.