Digital Verification Engineer - New Grad
Ciena
United States
Workplace: OnsiteFull timeUSD 79,300 - 126,700 annuallyFunction: Software EngineeringEducation: bachelorsSkills: ["SystemVerilog","SVA","UVM","Verilog","C","Testbench","Verifications"]Join Ciena as a Digital Verification Engineer working on the Wavelogic family of products, implementing verification strategies to thoroughly simulate and validate functional blocks. Read and interpret requirements, create test plans, build testbenches with SystemVerilog UVM and C, perform coverage-driven verification, and report progress within a collaborative team of engineers and architects.
