STAFF ENGINEER, DDEG Design Methodology
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Debugging","Teamwork","Analytical capability"]Own verification and end-to-end analysis of sophisticated full-chip gate-level DRAM designs, leveraging AI-based tools and automation to accelerate verification cycle time and improve debug efficiency. Build and maintain SV/UVM testbenches, stimulus, test vectors, and regressions to raise functional coverage across DDR4/LPDDR4/DDR5/LPDDR5 and emerging memory architectures. Simulate, analyze, and debug pre-silicon blocks and full chips, collaborate globally, and validate AI outputs against specs using simulations and coverage reports.
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