Verification Engineer

AMD
Markham
Workplace: HybridFull timeCAD 112,000 - 192,000 annuallyFunction: Software EngineeringEducation: bachelorsSkills: ["Analytical","Detail-oriented","Collaborative","Debugging","Ownership"]

Lead and contribute to verification of Network-on-Chip (NoC) IPs, subsystems, and SoC designs at block and subsystem level. Architect and develop simulation and/or formal verification environments to prove functional correctness. Build SystemVerilog/UVM testbenches, create constrained-random and directed environments, write SVA, and use industry formal tools. Partner with global design and architecture teams to debug issues, improve stimulus quality, perform coverage analysis, and drive verification closure.

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FursaFursa
AMD
AMD
2 days ago

Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Lead and contribute to verification of Network-on-Chip (NoC) IPs, subsystems, and SoC designs at block and subsystem level. Architect and develop simulation and/or formal verification environments to prove functional correctness. Build SystemVerilog/UVM testbenches, create constrained-random and directed environments, write SVA, and use industry formal tools. Partner with global design and architecture teams to debug issues, improve stimulus quality, perform coverage analysis, and drive verification closure.
Location: Markham
Workplace: Hybrid
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Lead and plan verification of complex digital design blocks by understanding architecture and specifications.
  • •Collaborate with architects and design engineers to define comprehensive verification test plans.
  • •Design and architect SystemVerilog and UVM testbenches for efficient design verification.
  • •Build and enhance constrained-random and/or directed verification environments and perform formal verification using SVA and formal tools.
  • •Debug with design engineers and perform coverage analysis to find verification holes and achieve coverage closure.

Pay and Benefits

Salary: CAD 112,000 - 192,000 annually

Key Requirements

  • •Strong SystemVerilog and UVM verification expertise for ASIC/SoC methodologies.
  • •Experience with constraint-random, coverage-driven verification and formal verification using SVA.
  • •Ability to verify complex digital designs, ideally including NoC architectures, and debug complex issues.
  • •Analytical, detail-oriented, and collaborative approach with experience driving verification closure.
  • •Bachelors or Masters degree in computer engineering or electrical engineering.
Experience:ASICSoCNoCFPGA
Education:Bachelor's in computer engineering/Electrical Engineering
Skills:AnalyticalDetail-orientedCollaborativeDebuggingOwnership
Tech Stack:System VerilogUVMSVAFormal verificationOVMVMMConstraint-random verificationCoverage-driven verificationSystemVerilog testbenchesSynopsys VCSCadence IESCadence IEVJasperSynopsys VC-FormalMagellanAXI3AXI4DDR4DDR5HBM

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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