STAFF ENGINEER, DDEG Design Methodology
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Debugging","Teamwork","Analytical capability","Judgment"]Own end-to-end verification and analysis of sophisticated full chip, gate-level custom DRAM designs, using AI-based tools and automation to accelerate verification cycles. Build and maintain test benches/test vectors, develop Verilog/SystemVerilog and UVM testbenches, and improve debug efficiency across simulation and silicon learning loops. Partner with global design/verification teams to create verification flows, provide pre-silicon block/full-chip debug support, and validate AI outputs against specs, simulations, and coverage.
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