Principal Design Engineer ( Layout Design )

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8-11 yearsEducation: bachelorsSkills: ["Communication","Documentation","Presentation","Analytical problem-solving","Team collaboration"]

Design custom layouts for next-generation, high-speed analog IPs such as SerDes, DDR/LPDDR, PCIe, HBM, and chiplets. Gather and translate requirements from circuit, digital, packaging, and foundry teams to deliver analog macros. Perform physical verifications including DRC, LVS, and electrical checks for LVS/ageing and reliability compliance. At the principal level, also lead a team to ensure successful IP delivery and adapt to evolving technology and foundry needs.

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Cadence Design Systems
Cadence Design Systems
1 month ago

Principal Design Engineer ( Layout Design )

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Last checked: 13 hours agoStatus: Live

Job Summary

Design custom layouts for next-generation, high-speed analog IPs such as SerDes, DDR/LPDDR, PCIe, HBM, and chiplets. Gather and translate requirements from circuit, digital, packaging, and foundry teams to deliver analog macros. Perform physical verifications including DRC, LVS, and electrical checks for LVS/ageing and reliability compliance. At the principal level, also lead a team to ensure successful IP delivery and adapt to evolving technology and foundry needs.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Create custom layout designs for next-gen high-speed IPs including SerDes/DDR/GDDR/LPDDR/PCIe/D2D/HBM/Ucie/chiplets.
  • •Collaborate with circuit-design, digital, packaging, and foundry stakeholders to deliver analog macros using a co-creation approach.
  • •Conduct physical verifications: full-spectrum foundry verifications and DRC variants.
  • •Run electrical checks such as LVS and ageing/reliability compliance.
  • •At the appropriate expertise level, lead a team of engineers and adapt to changing market, client, technology, and foundry needs.

Key Requirements

  • •8–11 years (or equivalent) experience in high-speed products and classical analog layout design.
  • •Hands-on layout experience with analog IP such as high-speed analog (SerDes), data converters, power management, and PLL.
  • •Experience with latest technology nodes such as 18a, 2nm, 3nm, 5nm, 7nm and below (desired).
  • •Knowledge of analog layout techniques, floorplan constraints, IP integration at chip level, including matching and shielding.
  • •Strong communication skills and documentation/presentation; scripting/automation experience is a plus.
Experience:8-11 yearsElectronic designAnalog IP
Education:Bachelor's in Electrical/Electronic
Skills:CommunicationDocumentationPresentationAnalytical problem-solvingTeam collaboration
Tech Stack:SerDesDDRGDDRLPDDRPcieD2DHBMUcieChipletsDRCLVSAgeingReliability ComplianceOpampsBandgapsDataconvertersLDOPLLFloorplan constraintsMatching

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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